Techniques for programming programmable logic array devices

US6384630B2 · kind B2 · utility

Assignee

• Altera Corporation · US

Inventors

• Richard G. Cliff · Milpitas, US
• Srinivas T. Reddy · Fremont, US
• Kerry Veenstra · San Jose, US
• Andreas Papaliolios · Sunnyvale, US
• Chiakang Sung · Milpitas, US
• Richard Shaw Terrill · San Jose, US
• Rina Raman · Los Altos, US
• Robert Richard Noel Bielby · Placerville, US

Key dates

• Filing date: Jan 12, 2001
• Grant date: May 7, 2002
• Expiry date: Jan 12, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/17748
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.