Architecture for handling internal voltages in a non-volatile memory, particularly in a single-voltage supply type of dual-work flash memory
US6385107B1 · kind B1 · utility
36Cited by
6References
10Claims
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Key dates
| Filing date | Nov 9, 2000 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Nov 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture handles internal voltages in a non-volatile memory array which is split into at least first and second mutually independent banks. The architecture includes first and second pluralities of generators for generating at least one of the internal voltages, which are separate from each other and connected to the first and second banks, respectively, of the nonvolatile memory array; and a control system connected to the pluralities of generators to handle the correct activation of the different generators in the different conditions of the memory array operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.