Power-off state storage apparatus and method
US6385120B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2001 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Dec 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for power-off state storage in an electronic device having a positive power supply includes a storage circuit comprising first and second storage capacitors and a write circuit having a plurality of N-type transistors coupled to the storage circuit. The write circuit is operable to write a data bit to the first and second storage capacitors. The power-off state storage circuit also has a sense amplifier connected to the storage circuit and that is operable to read the data bit stored by the storage capacitors. The first and second capacitors in the storage circuit are electrically isolated from the positive power supply such that when the positive power supply is terminated any charge stored on the first and second capacitors is prevented from discharging to the terminated power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.