System and method for concurrent placement of gates and associated wiring
US6385760B2 · kind B2 · utility
6Cited by
13References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1998 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Jun 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.