Method for adhering and sealing a silicon chip in an integrated circuit package
US6387729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2001 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Jul 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.