Methods of T-gate fabrication using a hybrid resist
US6387783B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1999 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Apr 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28581
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming a T-gate on a substrate are provided that employ a hybrid resist. The hybrid resist specifically is employed to define a base of the T-gate on the substrate with very high resolution. To define a base of the T-gate, a hybrid resist layer is deposited on the substrate. A mask having a reticle feature with an edge is provided and is positioned above the hybrid resist layer so that the edge of the reticle feature is above a desired location for the base of the T-gate. Thereafter, the hybrid resist layer is exposed to radiation through the mask, and the exposed hybrid resist layer is developed to define an opening therein for the base of the T-gate. Preferably the loop feature formed in the hybrid resist layer by the reticle feature during exposure is trimmed. The T-gate may be completed by employing any known T-gate fabrication techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.