Method of etching trenches for metallization of integrated circuit devices with a narrower width than the design mask profile

US6387798B1 · kind B1 · utility

Assignee

• Institute of Microelectronics · SG

Inventors

• Nelson Chou San Loke · Kuala Kangsar, MY
• Mukherjee-Roy Moitreyee · Singapore, SG
• Joseph Xie · Singapore, SG

Key dates

• Filing date: Jun 25, 2001
• Grant date: May 14, 2002
• Expiry date: Jun 25, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76804
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of etching trenches through a low-k material layer using a hard mask wherein the trenches are sized down from the mask size by etching without sacrificing a vertical trench profile is described. A low-k dielectric material is provided over a region to be contacted on a substrate. A hard mask layer is deposited overlying the dielectric material. A mask is formed over the hard mask layer wherein the mask has a first opening of a first width. A second opening is etched in the hard mask layer where it is exposed by the mask wherein the second opening has a second width smaller than the first width and wherein the second opening has inwardly sloping sidewalls. A trench is etched through the dielectric layer to the region to be contacted through the second opening whereby the trench has a width equal to the second width. The trench is filled with a metal layer to complete fabrication of the integrated circuit device.