Triple metal line 1T/1C ferroelectric memory device and method for fabrication thereof
US6388281B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2000 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Jul 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a triple metal line 1T/1C ferroelectric memory device and a method to make the same. A ferroelectric capacitor is connected to the transistor through a buried contact plug. An oxidation barrier layer lies between the contact plug and the lower electrode of the capacitor. A diffusion barrier layer covers the ferroelectric capacitor to prevent diffusion of material into or out of capacitor. As a result of forming the oxidation barrier layer, the contact plug is not exposed to the ambient oxygen atmosphere thereby providing a reliable ohmic contact between the contact plug and the lower electrode. Also, the memory device provides a triple interconnection structure made of metal, which improves device operation characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.