Method and apparatus for reducing the lock time of DLL
US6388480B1 · kind B1 · utility
53Cited by
7References
47Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2000 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Aug 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay element. When the first pulse reaches the end of the delay line, the status of the shift bits is frozen, and a starting point for a synchronization sequence begins at the transition point between toggled and retoggled shift bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.