Method and apparatus for ram built-in self test (BIST) address generation using bit-wise masking of counters
US6388930B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2001 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Sep 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a selected subset of memory addresses associated with a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the method includes configuring an address counter to generate addresses corresponding to locations within the memory array. A mask register is programmed with a series of masking bits, the value of the masking bits determining whether corresponding address bits in the address counter are masked or not masked. Any of the address bits in the address counter corresponding to a masked bit are masked from a counting operation performed by the address counter, thereby causing the address counter to generate the selected subset of memory addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.