Converification system and method
US6389379B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1998 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Jun 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The coverification system includes a reconfigurable computing system (hereinafter “RCC computing system”) and a reconfigurable computing hardware array (hereinafter “RCC hardware array”). In some embodiments, the target system and the external I/O devices are not necessary since they can be modeled in software. In other embodiments, the target system and the external I/O devices are actually coupled to the coverification system to obtain speed and use actual data, rather than simulated test bench data. The RCC computing system contains a CPU and memory for processing data for modeling the entire user design in software. The RCC computing system also contains clock logic (for clock edge detection and software clock generation), test bench processes for testing the user design, and device models for any I/O device that the user decides to model in software instead of using an actual physical I/O device. The user may decide to use actual I/O devices as well as modeled I/O devices in one debug session. The software clock is used as the external clock source for the target system and the external I/O devices to synchronize all data that is delivered between the c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.