Freezing mechanism for debugging
US6389557B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1998 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Sep 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for freezing a communication device in a debug mode has a clock control circuit arranged to produce an internal clock signal in response to an external clock signal. When a stop signal is asserted, the internal clock signal is fixed in its off state. As a result, operations of internal registers supplied with the internal clock signal freeze in a chosen state. A scan test may be performed to examine the internal registers in the chosen state. A bypass clock signal is supplied to control the internal clock signal so as to move the internal registers from one state to another. Thus, an event that causes an error may be recreated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.