Process for manufacturing a multi-layer circuit board
US6391210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2001 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Jul 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0554
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentiall…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.