Formation of arrays of microelectronic elements
US6391658B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1999 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Oct 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/10
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Arrays of microelectronic elements such as magnetorestive memory elements and FET's, including dual-gate FET's, are fabricated by methods involving a host wafer and a first wafer on which part of the microelectronic elements are separately formed. Conductive elements such as metal-filled vias are formed in the host wafer and extend to its surface. Hydrogen ions are implanted at a selected depth in the first wafer. After formation of selected portions of the microelectronic elements above the hyrogen ion implantation depth of the first wafer, the latter is bonded to the surface of the host wafer so that complementary parts of the two wafers can join to form the microelectronic elements. The first wafer is fractured at the hydrogen ion implantation depth and its lower portion is removed to allow for polishing and affixing of electrodes thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.