Inventor · Cupertino, CA, US

Roy E. Scheuerlein

271Patents
56h-index
97Co-inventors
93Inventor score

Filing activity: Dec 26, 1979 → Jan 14, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US5640343A Magnetic memory array using magnetic tunnel junction devices in the memory cells Physics 770 Expired
US7005350B2 Method for fabricating programmable memory array structures incorporating series-connected transistor strings Electricity 385 Expired
US7575973B2 Method of making three dimensional NAND memory Electricity 328 Active
US7233522B2 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same Electricity 287 Expired
US7177191B2 Integrated circuit including memory array incorporating multiple types of NAND string structures Physics 285 Expired
US7221588B2 Memory array incorporating memory cells arranged in NAND strings Electricity 239 Expired
US7023739B2 NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same Physics 233 Expired
US7851851B2 Three dimensional NAND memory Electricity 226 Active
US7514321B2 Method of making three dimensional NAND memory Electricity 221 Active
US7848145B2 Three dimensional NAND memory Physics 219 Active
US7808038B2 Method of making three dimensional NAND memory Electricity 217 Active
US7745265B2 Method of making three dimensional NAND memory Electricity 217 Active
US5793697A Read circuit for magnetic memory array using magnetic tunnel junction devices Physics 216 Expired
US7233024B2 Three-dimensional memory device incorporating segmented bit line memory array Emerging Cross-Sectional Technologies 210 Expired
US5991193A Voltage biasing for magnetic ram with magnetic tunnel memory cells Physics 194 Expired
US6391658B1 Formation of arrays of microelectronic elements Electricity 176 Expired
US6631085B2 Three-dimensional memory array incorporating serial chain diode stack Physics 168 Expired
US6879505B2 Word line arrangement having multi-layer word line segments for three-dimensional memory array Physics 154 Expired
US6005800A Magnetic memory array with paired asymmetric memory cells for improved write margin Physics 136 Expired
US7243203B2 Pipeline circuit for low latency memory Physics 132 Expired
US7829875B2 Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse Physics 123 Active
US7474000B2 High density contact to relaxed geometry layers Electricity 122 Expired
US7426128B2 Switchable resistive memory with opposite polarity write pulses Physics 121 Expired
US7859884B2 Structure and method for biasing phase change memory array for reliable writing Electricity 113 Active
US7023260B2 Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor Electricity 111 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.