Embedded structures to provide electrical testing for via to via and interface layer alignment as well as for conductive interface electrical integrity in multilayer devices
US6391669B1 · kind B1 · utility
32Cited by
10References
26Claims
0Family size
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Key dates
| Filing date | Jun 21, 2000 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Jun 21, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49004
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Multilayer substrates, are fabricated with the incorporation therein of non-destructive test structures utilized to provide visual and electrical test data to facilitate the ascertainment and assessment of potential electrical interface failures. Furthermore, there are provided embedded structures in multilayer substrates, such as are employed in chip carrier packaging, so as to facilitate electrical testing for via to via alignment and interface layer alignment, and to enable the testing of conductive interface electrical integrity of multilayer electrical devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.