Method for forming a plug or damascene trench on a semiconductor device
US6391763B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 2000 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Jun 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a plug or damascene trench on a semiconductor device includes the following steps: depositing a dielectric layer consisting of hydrogen silsesquioxane (HSQ) on the semiconductor device, depositing a mask layer consisting of a hard mask material on the dielectric layer, removing a portion of the mask layer and defining the remaining portion of the mask layer as a hard mask, curing the portion of the dielectric layer not covered with the hard mask by e-beam; removing the portion of the dielectric layer not being cured by e-beam with a wet etch process to create an opening in the dielectric layer, wherein the wet etch rate of the portion of the dielectric layer being e-beam cured is significantly lower than that of the portion of the dielectric layer not being e-beam cured, and filling the opening in the dielectric layer with a kind of metal material or polysilicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.