Semiconductor device with DMOS, BJT and CMOS structures
US6392275B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1999 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Oct 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/105
Abstract
A semiconductor device having a substrate composed of a DMOS transistor, a complementary MOS (CMOS) transistor and a bipolar junction transistor is disclosed. A highly-doped bottom layer is formed on a lower edge of a body region of the DMOS transistor, a heavily doped bottom layer of a conductivity type opposite to that of the substrate is formed on a lower edge of source and drain regions of the CMOS transistor, and a highly-doped bottom layer of the same conductivity type as that of the substrate is formed on a lower portion of an intrinsic base region of the bipolar junction transistor, to thereby enhance the electrical characteristics of devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.