Integrated circuit and associated fabrication process
US6392299B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 24, 1999 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Nov 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect level includes upper and lower partial levels having respective conductive lines offset heightwise from each other. The interconnect level further includes respective dielectric portions separating adjacent conductive lines and extends above and below the conductive lines. At least one descending via connects a conductive line of the upper partial level with a lower element located below the dielectric portions of the interconnect level. The at least one descending via extends through the dielectric portions separating adjacent conductive lines of the lower partial level. At least one ascending via connects a conductive line of the lower partial level with an upper element located above the dielectric portions of the interconnect level. At least one ascending via extends through the dielectric portions separating adjacent conductive lines of the upper partial level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.