Philippe Gayet
10Patents
5h-index
10Co-inventors
59Inventor score
Filing activity: Jul 19, 1991 → Aug 29, 2003
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6239025A | High aspect ratio contact structure for use in integrated circuits | Electricity | 16 | Expired |
| US6451669B2 | Method of forming insulated metal interconnections in integrated circuits | Electricity | 15 | Expired |
| US5736451A | Method of forming planar isolation in integrated circuits | Electricity | 10 | Expired |
| US6580130B1 | Process for producing a resistor in an integrated circuit and corresponding integrated static random access memory device having four transistors and two resistors | Electricity | 7 | Expired |
| US6392299B1 | Integrated circuit and associated fabrication process | Electricity | 7 | Expired |
| US6762497B2 | Integrated circuit with stop layer and associated fabrication process | Electricity | 2 | Expired |
| US6355552B1 | Integrated circuit with stop layer and associated fabrication process | Electricity | 2 | Expired |
| US5186786A | Method for determining the complete elimination of a thin layer on a non planar substrate | Electricity | 1 | Expired |
| US7064053B2 | Process for fabricating an electrical circuit comprising a polishing step | Electricity | 1 | Expired |
| US6525393B1 | Semiconductor substrate having an isolation region | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.