Differential input buffer bias circuit
US6392453B1 · kind B1 · utility
13Cited by
1References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2001 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Jun 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated differential buffer circuit and its method of operation are described in which the buffer circuit has an internal bias line for controlling the supply of voltage to the buffer circuit. When the buffer circuit is first enabled, a start voltage is initially applied to the bias line and then removed to ensure proper operation of the buffer circuit when first enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.