Burst-configurable data bus
US6393500B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1999 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Aug 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is presented for improving the efficiency of data transactions over a computer system data bus. Bus efficiency is improved by providing a bus master with information to adjust the length and width of burst transactions over the bus to/from target devices. If a particular target device is not capable of transacting a full-length, full-width burst over the bus, then the bus master configures a burst to exploit the bursting capabilities of that particular target device. The bus master apparatus includes slave configuration logic that is configured to store a burst transaction capability corresponding to each slave device connected to the bus. The bus master apparatus also has transaction control logic. The transaction control logic is coupled to the slave configuration logic and uses the information to vary burst width and length for a transaction to a specific slave device according to the slave's burst transaction capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.