Method and system for performing pseudo-random testing of an integrated circuit
US6393594B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1999 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Aug 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3183
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.