Inventor · Austin, TX, US

Larry Scott Leitner

20Patents
8h-index
26Co-inventors
75Inventor score

Filing activity: Aug 11, 1999 → Oct 6, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US7343476B2 Intelligent SMT thread hang detect taking into account shared resource contention/blocking Physics 66 Expired
US6393594B1 Method and system for performing pseudo-random testing of an integrated circuit Physics 35 Expired
US6633838B1 Multi-state logic analyzer integral to a microprocessor Physics 35 Expired
US6802031B2 Method and apparatus for increasing the effectiveness of system debug and analysis Physics 18 Expired
US6857083B2 Method and system for triggering a debugging unit Physics 13 Expired
US7657893B2 Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor Physics 12 Active
US6543003B1 Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor Physics 9 Expired
US7725685B2 Intelligent SMT thread hang detect taking into account shared resource contention/blocking Physics 8 Active
US6529979B1 Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgement Physics 7 Expired
US8271738B2 Apparatus for operating cache-inhibited memory mapped commands to access registers Physics 5 Active
US7574581B2 Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components Physics 2 Active
US7392350B2 Method to operate cache-inhibited memory mapped commands to access registers Physics 2 Expired
US9003417B2 Processor with resource usage counters for per-thread accounting Physics 1 Active
US11301392B2 Address translation cache invalidation in a microprocessor Physics 0 Active
US11243864B2 Identifying translation errors Physics 0 Active
US8209698B2 Processor core with per-thread resource usage accounting logic Physics 0 Active
US11080122B2 Software-invisible interrupt for a microprocessor Physics 0 Active
US10915456B2 Address translation cache invalidation in a microprocessor Physics 0 Active
US8639855B2 Information collection and storage for single core chips to 'N core chips Physics 0 Active
US7996703B2 Method and apparatus to avoid power transients during a microprocessor test Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.