Capacitor plate formation in a mixed analog-nonvolatile memory device
US6395590B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 15, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Sep 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
Abstract
A process is provided for manufacturing a semiconductor device. A lower polycrystalline silicon layer is deposited on a substrate surface and on one or more structures that protrude from the substrate surface. A dielectric layer is formed on the lower polycrystalline silicon layer. An upper polycrystalline silicon layer is deposited on the dielectric layer. The upper polycrystalline silicon layer is patterned to form one or more upper capacitor plates. Next, the exposed portions of the dielectric layer not covered by the one or more upper capacitor plates are removed. After the steps of patterning the upper polycrystalline silicon area and removing the exposed portions of the dielectric layer, the lower polycrystalline silicon layer is patterned to form at least one or more lower capacitor plates. Each lower capacitor plate underlies a corresponding one of the upper capacitor plates and a portion of the dielectric layer covered by the corresponding upper capacitor plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.