Selective substrate implant process for decoupling analog and digital grounds
US6395591B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Dec 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.