Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration
US6395593B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Apr 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of minimizing parasitics in an MOS device caused by the formation of a bipolar transistor within the MOS devices and the device, primarily for a polyphase bridge circuit. For the low side device, a substrate of a first conductivity type is provided having a first buried layer of opposite conductivity type thereon. A second buried layer of the first conductivity type is formed over the first buried layer and a further layer of the first conductivity type is formed over the second buried layer. A sinker extending through the further layer to the first buried layer is formed to isolate the second buried layer and the further layer from the substrate. Formation of an MOS device in the further layer including source, drain and gate regions is completed and the sinker is connected to a source terminal of the device. The second buried layer is formed either by coimplanting a p-type dopant and an n-type dopant with one of the dopant having a higher diffusion rate than the other or by implanting and diffusing one of the two dopants first to form one layer and then implanting and diffusing the other dopant to form the second layer. The preferred dopants are boron as the p-type dopan…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.