Method for forming a lower electrode for use in a semiconductor device
US6395601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Dec 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device can form a thick lower electrode made of Pt. The method begins with the preparation of an active matrix provided with at least one diffusion region and an insulating layer formed thereon. Thereafter, the insulating layer is patterned into a predetermined configuration, thereby exposing the diffusion region and a metal silicide film is formed on the exposed diffusion region. And then, a barrier metal is formed on the metal silicide and a seed layer is formed on the active matrix including the barrier metal. In an ensuing step, a dummy oxide layer is formed on the seed layer and a dummy oxide layer is patterned into a preset configuration, thereby exposing portions of the seed layer which are located above the barrier metal. Next, the exposed portions of the seed layer are filled with a conductive material to a predetermined thickness. In a following step, the dummy oxide layer and the seed layer which are not covered with the conductive material is removed by using an etch technique to obtain a lower electrode structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.