Reduction of tungsten damascene residue
US6395635B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1998 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Dec 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CMP process is provided for the reduction of tungsten damascene residue and the elimination of surface scratch within the surface that is being polished. A three step polishing procedure of the ILD is followed by a two step buffing procedure of the ILD. The three step polishing procedure reduces the device defect count by eliminating damascene residue from the polished surface. The two step buffing procedure reduces micro scratch within the polished surface thus improving device throughput. A two step buffing procedure is applied to the IMD. Oxide buffing is applied and consists of a three step polishing procedure followed by a two step buffing procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.