Testing of multilevel semiconductor memory
US6396742B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jul 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.