Flash memory with dynamic refresh
US6396744B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Apr 25, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3431
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-bit-per-cell non-volatile memory periodically reads and rewrites data and thereby refreshes threshold voltages and removes the effects of threshold voltage drift. Accordingly, threshold voltages are kept in narrower ranges, and the narrow ranges allow more distinct levels for data values and allows storage of more bits per cell. A refresh interval is according to the size of windows for different multi-bit values and the measured or expected rate of threshold voltage drift. An on-chip refresh timer and arbitration logic selects when to initiate a refresh operation. A refresh can use a data buffer for temporary storage or can directly write data from one memory location to another. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In particular embodiments, shifts sectors-sized data blocks cyclically among sectors in an array, a bank, or an entire memory or alternatively shifts the data blocks between two configurations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.