Multi Level Memory Technology
20Patents
0Active
20Granted
32Portfolio score
Filing activity: Nov 5, 1999 → Sep 30, 2004
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6259627A | Read and write operations using constant row line voltage and variable column line load | Physics | 267 | Expired |
| US6532556B1 | Data management for multi-bit-per-cell memories | Physics | 235 | Expired |
| US6278633A | High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations | Physics | 183 | Expired |
| US6466476B1 | Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell | Physics | 138 | Expired |
| US6363008B1 | Multi-bit-cell non-volatile memory with maximized data capacity | Physics | 124 | Expired |
| US6882567B1 | Parallel programming of multiple-bit-per-cell memory cells on a continuous word line | Physics | 116 | Expired |
| US6558967B1 | Multi-bit-per-cell memory system with numbers of bits per cell set by testing of memory units | Physics | 103 | Expired |
| US6522586B2 | Dynamic refresh that changes the physical storage locations of data in flash memory | Physics | 62 | Expired |
| US6614685B2 | Flash memory array partitioning architectures | Physics | 56 | Expired |
| US6330185A | High bandwidth multi-level flash memory using dummy memory accesses to improve precision when writing or reading a data stream | Physics | 41 | Expired |
| US6396744B1 | Flash memory with dynamic refresh | Physics | 40 | Expired |
| US6906951B2 | Bit line reference circuits for binary and multiple-bit-per-cell memories | Physics | 29 | Expired |
| US6662263B1 | Sectorless flash memory architecture | Physics | 27 | Expired |
| US6570810B2 | Contactless flash memory with buried diffusion bit/virtual ground lines | Physics | 26 | Expired |
| US6856568B1 | Refresh operations that change address mappings in a non-volatile memory | Physics | 25 | Expired |
| US6480422B1 | Contactless flash memory with shared buried diffusion bit line architecture | Electricity | 18 | Expired |
| US6747896B2 | Bi-directional floating gate nonvolatile memory | Electricity | 17 | Expired |
| US6914820B1 | Erasing storage nodes in a bi-directional nonvolatile memory cell | Electricity | 9 | Expired |
| US6826084B1 | Accessing individual storage nodes in a bi-directional nonvolatile memory cell | Electricity | 4 | Expired |
| US6754128B2 | Non-volatile memory operations that change a mapping between physical and logical addresses when restoring data | Physics | 3 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.