Memory having a redundancy scheme to allow one fuse to blow per faulty memory column
US6396760B1 · kind B1 · utility
29Cited by
6References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2001 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Mar 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method in which a single fuse is asserted in a memory bank having a redundancy memory column structure. The assertion of the single fuse causes two or more of the input-output circuits to shift away from a primary memory column to a substitute memory column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.