Niranjan Behera
14Patents
6h-index
13Co-inventors
63Inventor score
Filing activity: Mar 16, 2001 → May 4, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6396760B1 | Memory having a redundancy scheme to allow one fuse to blow per faulty memory column | Physics | 29 | Expired |
| US7139204B1 | Method and system for testing a dual-port memory at speed in a stressed environment | Physics | 24 | Expired |
| US6519202B1 | Method and apparatus to change the amount of redundant memory column and fuses associated with a memory device | Physics | 16 | Expired |
| US7415641B1 | System and method for repairing a memory | Physics | 16 | Expired |
| US7031866B1 | System and method for testing a memory | Physics | 8 | Expired |
| US7940550B2 | Systems and methods for reducing memory array leakage in high capacity memories by selective biasing | Physics | 6 | Active |
| US6646933B1 | Method and apparatus to reduce the amount of redundant memory column and fuses associated with a memory device | Physics | 4 | Expired |
| US7788551B2 | System and method for repairing a memory | Physics | 1 | Active |
| US7539590B2 | System and method for testing a memory | Physics | 1 | Expired |
| US11670361B2 | Sequential delay enabler timer circuit for low voltage operation for SRAMs | Physics | 0 | Active |
| US9966131B2 | Using sense amplifier as a write booster in memory operating with a large dual rail voltage supply differential | Physics | 0 | Active |
| US11481255B2 | Management of memory pages for a set of non-consecutive work elements in work queue designated by a sliding window for execution on a coherent accelerator | Physics | 0 | Active |
| US7904766B1 | Statistical yield of a system-on-a-chip | Physics | 0 | Active |
| US12340865B2 | Reduced circuit area memory device with a half-word memory architecture | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.