Redundant dual bank architecture for a simultaneous operation flash memory
US6397313B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 4, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Aug 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses sector-based redundancy that is capable of making repairs using a plurality of redundant columns of memory cells in a dual bank memory device during simultaneous operation. The simultaneous operation memory device includes a plurality of redundant blocks that can be configured to be located in an upper bank or a sliding lower bank. The redundant blocks are comprised of sectors and each sector contains columns of memory cells. During simultaneous operation, the memory device is capable of reading the columns of memory cells in one bank and writing columns of memory cells in the other bank at the same time. In addition, the simultaneous operation memory device uses sector-based redundancy to repair columns of memory cells that are defective in one bank by electrically exchanging them with redundant columns of memory cells and, at the same time, repair columns of memory cells that are defective in the other bank. The dual bank sector-based redundancy includes a plurality of address CAM circuits that are configurably associated with the redundant blocks based on the bank location of the redundant blocks. The address CAM circuits are configured by a redun…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.