Methods and apparatuses for binning partially completed integrated circuits based upon test results
US6399400B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1999 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Mar 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate array integrated circuit wafer is formed having M−N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M−N generic metal interconnection layers. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. In another embodiment, all M layers are deposited prior to performance and/or electrical testing; however, the Mth layer is not etched within the active die area prior to performance and/or electrical testing. Subsequent to binning based upon the test results, the final customization is performed by etching the Mth metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.