Ultra high density integrated circuit BLP stack and method for fabricating the same
US6399420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | May 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
BLP stack is disclosed which has a higher reliability and a less area of mounting for providing a denser package, including a first package having external power connection leads each started to be exposed through a bottom thereof and extended to a top surface through a side surface inclusive of bottom lead portions on a bottom surface, side lead portions on a side surface, and upper lead portions on a top surface, and a second package having external power connection leads started to be exposed through a bottom thereof and brought into contact with the external power connection leads on the first package to be electrically connected thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.