Enhanced side-wall stacked capacitor
US6399437B1 · kind B1 · utility
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1References
14Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 18, 1998 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jun 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method of forming a stacked capacitor having improved capacitance in a dynamic random access memory device is provided wherein and additional pad polysilicon layer is deposited prior to the forming of the capacitor cell contact area such that the side-wall of the capacitor cell can be increased. The increased side-wall thickness of the capacitor cell leads to an improved capacitance value for the cell. The present invention also provides a stacked capacitor formed in a semiconductor device that contains an additional pad polysilicon layer for increasing the thickness of the capacitor side-wall and subsequently its capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.