Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor
US6399447B1 · kind B1 · utility
32Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jul 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.