Semiconductor device having gate spacer containing conductive layer and manufacturing method therefor
US6399451B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1999 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Sep 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device with a gate spacer containing a conductive layer, and a manufacturing method. A first spacer insulation layer is formed on a semiconductor substrate where a gate electrode is formed. Then, the first spacer insulation layer is etched to cover the side walls of the gate electrode. A conductive spacer film is subsequently formed on the resultant structure and is over-etched to form a conductive spacer that covers the first spacer insulation layer. In this step, the gate electrode is partially consumed to make the top of the first spacer insulation layer higher than the gate electrode. Also, an upper portion of the first spacer insulation layer is not comparatively etched due to an etching selectivity. This structure avoids shorts between the conductive spacer and the gate electrode. A second spacer insulation layer is then formed on the conductive spacer. As a result, degradation of characteristics of the semiconductor device, due to hot electrons trapped within a gate insulation layer and a spacer area, can be suppressed. Also, the silicide layer can be formed on the gate electrode, thereby increasing the operational speed of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.