Addition of planarizing dielectric layer to reduce a dishing phenomena experienced during a chemical mechanical procedure used in the formation of shallow trench isolation regions
US6399461B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jan 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating silicon oxide filled, shallow trench isolation (STI), regions, in a semiconductor substrate, featuring the use of a disposable boro-phosphosilicate glass (BPSG), layer, used for planarization of various width, silicon oxide filled, STI regions, has been developed. After completely filling all STI shapes with a high density plasma (HDP), silicon oxide layer, resulting in a non-planar, HDP silicon oxide top surface topography, a BPSG layer is deposited. An anneal procedure is then performed resulting in a planar top surface topography of the reflowed BPSG layer. A chemical mechanical polishing procedure is next employed to remove the planar, reflowed BPSG layer, and portions of the underlying HDP silicon oxide, from the top surface of a silicon nitride stop layer, resulting in a planar top surface topography for all silicon oxide filled, insulator regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.