Process for fabricating a planar heterostructure
US6399502B1 · kind B1 · utility
14Cited by
2References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The process comprises:etching, in a semiconductor substrate (2), at least one trench (3) with predetermined width and depth; depositing, on the substrate and in the trench, a stack of successive and alternate layers of Si1−xGex (0<x≦1) and Si (5-8), the number and the thickness of which depend on the final use intended for the heterostructure; and chemical-mechanical polishing in order to obtain a final heterostructure having a plane upper main surface, level with which the stack layers deposited in the trench are flush.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.