Method for metal etch using a dielectric hard mask
US6399508B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jan 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for etching metal-comprising layers within a semiconductor structure using an inorganic dielectric hard masking layer. A typical stacked metal layer structure for practicing the method of the invention includes, from top to bottom, an inorganic dielectric hard masking layer, an anti-reflection (ARC) layer, a conductive layer, a diffusion barrier layer, and a dielectric layer, all deposited on a surface of a silicon substrate. When the inorganic dielectric hard masking layer is pattern etched, using an overlying photoresist mask, residual photoresist is removed prior to subsequent steps in which underlying metal-comprising layers are etched. The metal-comprising layers are then etched using a chlorine-based plasma, using the inorganic dielectric layer as a hard mask. The method of the invention provides good etch profile control without undesirable polymeric contamination. The selectivity for etching the underlying metal-comprising layers relative to the dielectric hard masking layer is at least 10:1. The higher selectivity ratio means that a thinner masking layer can be used, and etch resolution is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.