Thin film transistor with reduced metal impurities
US6399959B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Mar 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6758
Abstract
A structure for forming thin film transistor with reduced metal impurities. The structure at least includes the following steps. First of all, an insulation substrate. Then, an insulating gettering layer on the insulation substrate, wherein the amorphous silicon layer defines an active area, and a channel region on the insulating gettering layer, a source region on the insulating gettering layer adjacent to the channel region, a drain region on the insulating gettering layer adjacent to the channel region and opposite to the source region, and a gate on the channel region, wherein the source, drain, insulating gettering layer and channel region are components of a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.