Radiation hardened silicon-on-insulator (SOI) transistor having a body contact
US6399989B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Aug 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region. These diffusions are ohmically connected to the body region via a body contact, and these diffusions are also connected to the source region by a self-aligned salicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.