Isolated well ESD device

US6399990B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ciaran J. Brennan · South Burlington, US
• Mark D. Jacunski · Colchester, US
• Michael Killian · South Burlington, US
• William R. Tonti · South Burlington, US

Key dates

• Filing date: Mar 21, 2000
• Grant date: Jun 4, 2002
• Expiry date: Mar 21, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

The present invention relates generally to protection of integrated circuits from electrostatic discharges and more specifically to the use of devices formed in isolated well regions for electrostatic discharge protection. One aspect of the present invention is an ESD protection circuit that includes a first FET and a second FET. The drain of the first FET is coupled to an ESD susceptible node and the source of the first FET is coupled to a first voltage terminal. The gate and a well of the first FET are coupled together and to the drain of the second FET. The source of the second FET is coupled to the first voltage terminal. The gate of the second FET is coupled to a second voltage terminal. The second voltage terminal is connected to a voltage source that is at the first voltage when the circuit is not powered, and at a voltage above the threshold voltage of the second FET when the circuit is powered. The well in which the first FET is formed is electrically isolated from other wells in the substrate. The electrical isolation surrounding the well includes (1) a second-type dopant isolation regions in a first type substrate surrounding and abutting the well, (2) a substrate doped …