Leadless semiconductor package
US6400004B1 · kind B1 · utility
272Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Aug 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A leadless semiconductor package mainly comprises a semiconductor chip disposed on a die pad and electrically connected to a plurality of leads arranged around the die pad. There are a plurality of tie bars connected to the die pad. The lower surface of each lead has an indentation formed corresponding to one of the bottom edges of the package. The semiconductor chip, the leads and the tie bars are encapsulated in a package body wherein the lower surface of each lead is exposed from the bottom surface of the package except the indentation thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.