Method of testing semiconductor integrated circuits and testing board for use therein
US6400175B2 · kind B2 · utility
2Cited by
4References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Mar 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing semiconductor integrated circuits comprises the step of simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to the respective testing electrodes of the semiconductor integrated circuit elements. The simultaneous testing step includes the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via PTC elements provided for the semiconductor integrated circuit elements in a one-to-one relationship.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.