Programmable delay element and synchronous DRAM using the same
US6400202B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Nov 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.