Sub-package bypass capacitor mounting for an array packaged integrated circuit
US6400576B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1999 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Apr 5, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node. These vias preferably are spaced-apart a distance &Dgr;X corresponding to the distance between first and second connections on the bypass capacitor although sub-mm offsets in a via at connections may be used to accommodate differing connection pitches. The bypass capacitor connections are coupled to the lower surfaces of the first and second vias, at the lower surface of the LGA package. When the package is …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.